1. Field of the Invention
The present invention relates generally to semiconductor devices using a substrate formed of two semiconductor substrates joined such as a silicon wafer and manufacturing methods thereof, and more specifically, to a so-called Bi-CMOS semiconductor device in which a bipolar transistor and a field effect transistor are formed using two kinds of semiconductor substrates of different oxygen concentrations and a manufacturing method thereof.
2. Description of the Background Art
Recently, silicon wafers are often used for semiconductor substrates in manufacturing semiconductor devices. Methods of manufacturing silicon wafers are roughly classified into CZ method (Czochralski method), FZ method (Floating Zone method), and MCZ method (Magnetic-field-applied Czochralski method). Silicon wafers manufactured according these three methods posses the following properties, respectively.
(i) CZ silicon wafer PA1 Oxygen concentration: 1.0-1.8.times.10.sup.18 atoms/cm.sup.3 PA1 High in mechanical strength PA1 (ii) MCZ silicon wafer PA1 Oxygen concentration: 2-8.times.10.sup.17 atoms/cm.sup.3 PA1 Medium in mechanical strength PA1 (iii) FZ silicon wafer PA1 Oxygen concentration: &lt;1.times.10.sup.16 atoms/cm.sup.3 PA1 Low in mechanical strength
Among the above-stated three kinds of silicon wafers, mostly used for semiconductor substrates for use in large scale integrated circuit devices (LSI) recently are silicon wafers manufactured according to the CZ method. Especially in the case of a silicon wafer having a diameter of 8 inch or larger, use of a silicon wafer manufactured by the CZ method is inevitable for its strength so that the wafer will not be damaged in a manufacturing process.
When a wafer is manufactured by the CZ method, a quartz crucible is generally used. Accordingly, oxygen is supplied from the silicon crucible to silicon monocrystal in the manufacture, and a silicon wafer having a high oxygen concentration in the range from 1.0 to 1.8.times.10.sup.18 atoms/cm.sup.3 is produced. With oxygen taken up high in concentration, the mechanical strength of the wafer itself is enhanced. Therefore, a CZ wafer can be used for a wafer with a larger diameter for the purpose of improving productivity.
As described above, a CZ silicon wafer has a high oxygen concentration in the range from 1.0 to 1.8.times.10.sup.18 atoms/cm.sup.3. Accordingly, if a silicon oxide film is formed on a CZ silicon wafer, the silicon oxide film will have many defects. Therefore, when a silicon oxide film is used for a gate oxide film for a field effect transistor, for example, the breakdown voltage of the oxide film degrades in accordance with reduction of the size of a semiconductor device to be formed in a silicon wafer.
According to the FZ method, a silicon wafer having a low oxygen concentration can be manufactured. However, the mechanical strength of an FZ silicon wafer is poor as compared to a CZ silicon wafer because of its low oxygen concentration. Therefore, subjected to a treatment with a number of heat histories, an FZ silicon wafer is prone to be damaged. On the other hand, a high quality silicon oxide film with few defects can be formed on the FZ silicon wafer because of its low oxygen concentration.
In Japanese Patent Laying-Open No. 2-46770, a semiconductor device of SOI structure is proposed which use a substrate formed of a CZ silicon wafer of high oxygen concentration and an FZ silicon wafer of low concentration thereon joined with each other. According to the semiconductor device, the property of a gate oxide film can be improved by forming a silicon oxide film on the FZ silicon wafer of low oxygen concentration even if size reduction further precedes. Furthermore, the CZ silicon wafer provides a high mechanical strength, and increase in the diameters of wafers can be achieved in order to further improve productivity.
A method of manufacturing a substrate for a semiconductor device having two silicon wafers directly joined with each other is, for example, disclosed in Japanese Patent Laying-Open No. 2-183510.
Formation of an MOS semiconductor device including a field effect transistor having a substrate of a CZ silicon wafer and an FZ silicon wafer joined thereon provides a semiconductor device free from degradation in electrical characteristics by improvement of the breakdown voltage of a gate oxide film, etc., even if size reduction further proceeds. However, when a so-called Bi-CMOS semiconductor device in which a bipolar transistor and a field effect transistor are formed within a single substrate is formed on the above-stated joined FZ silicon wafer, the following problem is encountered. The problem will be further described while sequentially describing steps in a manufacturing method of a Bi-CMOS semiconductor device.
FIGS. 22-33 are partial cross sectional views sequentially showing manufacturing steps for forming a Bi-CMOS semiconductor device in an FZ silicon wafer joined on a CZ silicon wafer.
A silicon wafer is manufactured according to the CZ method. Another silicon wafer is manufactured according to the FZ method. The surface of each of the silicon wafers is washed, highly cleaned, and made hydrophilic. Thus treated CZ silicon wafer and FZ silicon wafer have their surfaces mechanically joined with each other. Thereafter, the joined wafers are subjected to heat treatment at a temperature in the range from 500.degree. to 1000.degree. C. and a dehydration condensation reaction takes place between the joined surfaces of CZ silicon wafer and FZ silicon wafer. Control of the heat treatment permits the joining of the CZ silicon wafer and the FZ silicon wafer to be enhanced. Thus, as shown in FIG. 22, a silicon substrate formed of a p type CZ silicon wafer 100 and a p type FZ silicon wafer 300a thereon joined with each other is manufactured.
Referring to FIG. 23, p type and n type impurity ions each in a dose about in the range from 10.sup.15 -10.sup.16 /cm.sup.2 are introduced into prescribed regions of the FZ silicon wafer 300a. Thereafter, heat treatment at a temperature from 700.degree. to 1100.degree. C. is conducted, whereby n.sup.+ buried diffusion layers 371, 374 and p.sup.+ buried diffusion layers 372, 373 are formed.
Referring to FIG. 24, an n.sup.- epitaxial layer 400 having a thickness in the range from 2 to 10 .mu.m is formed at a temperature in the range from 650.degree. to 1100.degree. C. on a surface of the FZ silicon wafer 300a.
As shown in FIG. 25, n type and p type impurity ions each in a dose of about in the range from 10.sup.12 to 10.sup.13 /cm.sup.2 are implanted into prescribed regions of the n.sup.- epitaxial layer 400. Thereafter, lamp annealing treatment is conducted at a temperature in the range from 600.degree. to 1000.degree. C. and n type well regions 401, 403, 405, and p type well regions 402, 404 are formed as a result. Thus, the well regions are formed as CMOS transistor formation regions.
As shown in FIG. 26, p type impurity ions in a dose of about in the range from 10.sup.12 to 10.sup.14 /cm.sup.2 are implanted in to the p type well region 402. Thereafter, lamp annealing treatment is conducted at a temperature in the range from 600.degree. to 1000.degree. C., and a p type isolation region formed of a p.sup.+ region 402, a p.sup.- region 406, and a p.sup.+ buried diffusion layer 372 is formed as a result.
Referring to FIG. 27, isolation oxide films 407, 408, 409 are formed so as to isolate a prescribed element formation region in the n.sup.- epitaxial layer 400. At that time, n regions 410, 411, 413, and a p region 412 are formed.
Referring to FIG. 28, n type impurity ions in a dose of about in the range from 10.sup.14 to 10.sup.17 /cm.sup.2 are implanted into a region of the n region 410. Thereafter, lamp annealing treatment is conducted at a temperature in the range from 600.degree. to 1000.degree. C., and an n.sup.+ collector wall 414 is formed as a result.
As shown in FIG. 29, gate oxide films 415 and 416 are formed in the p region 412 and the n region 413, respectively. Gate electrodes 417 and 418 having a polycide structure are formed on the gate oxide films 415 and 416, respectively. Using the gate electrode 417 or 418 as mask, n type and p type impurity ions each in a dose about in the range from 10.sup.15 to 10.sup.16 /cm.sup.2 are implanted. Thereafter, lamp annealing treatment is conducted at a temperature in the range from 600.degree. to 1000.degree. C., and n type source/drain regions 419 and p type source/drain regions 420 are formed as a result. Thus, an n channel MOS transistor 450 and a p channel MOS 460 are formed.
As shown in FIG. 30, p type impurity ions in a dose about in the range from 10.sup.13 to 10.sup.15 /cm.sup.2 are implanted into the n region 410. Thereafter, lamp annealing treatment is conducted at a temperature in the range from 600.degree. to 1000.degree. C. thereby forming a p.sup.+ base region 421.
As shown in FIG. 31, n type impurity ions in a dose about in the range from 10.sup.15 to 10.sup.16 /cm.sup.2 are implanted into a region of the p.sup.+ base region 421. Thereafter, lamp annealing treatment is conducted at a temperature in the range from 600.degree. to 1000.degree. C., thereby forming an n.sup.+ emitter region 422.
An npn bipolar transistor 470 is thus formed.
As shown in FIG. 32, an interlayer insulating film 423 formed of an oxide film is formed on the entire surface of the FZ silicon wafer 300a, covering the bipolar transistor 470, the n channel MOS transistor 450, and the p channel MOS transistor 460.
Finally, as shown in FIG. 33, contact holes are made in the interlayer insulating film 423. Through the contact holes, aluminum interconnection layers 424, 425, 426, 427, 428, 429, and 430 are formed in contact with the surfaces of the collector region, the emitter region, the base region, the source region, and the drain region, respectively. As described above, a Bi-CMOS semiconductor device is formed in a substrate formed of the CZ silicon wafer 100 and the FZ silicon wafer 300a thereon joined with each other.
In the above-stated manufacturing steps, the epitaxial layer 400 is formed on the FZ silicon wafer 300a in order to form a bipolar transistor. At that time, a slip line is produced in the silicon wafer. FIG. 34 is a plan view showing slip lines produced in forming the epitaxial layer on the FZ silicon wafer 300a. FIG. 34 shows at (A) slip lines produced in a silicon wafer surface orientation (100). FIG. 34 shows at (B) slip line produced in a silicon wafer surface orientation (111). 380 represents an orientation flat. As can be seen from (A), slip lines 501 are produced in the peripheral portion of the FZ silicon wafer 300a. Referring to (B), it is observed that slip lines 502 formed in the peripheral part of the FZ silicon wafer 300a form a prescribed angle. Such a slip line is considered to be a gathering of dislocations each as a lattice defect of crystal.
FIG. 35 is an enlarged cross sectional view showing a bipolar transistor formed in an epitaxial layer including a slip line as described above. Referring to FIG. 33, a p.sup.+ base region 421 is formed in an n.sup.+ epitaxial layer 400. An n.sup.+ emitter region 422 is formed in the p.sup.+ base region 421. A depletion layer 431 is formed between the p.sup.+ base region 421 and the n.sup.+ emitter region 422. In this case, a slip line 500 extends from the p.sup.+ base region 421 to n.sup.+ emitter region 422. With the slip line 500 existing in a pn junction in this manner, current leakage is likely to take place. As a result, the electrical characteristic of the bipolar transistor deteriorates, resulting in an erroneous operation of the transistor. Accordingly, faulty Bi-CMOS semiconductor devices are produced. Faulty Bi-CMOS semiconductor devices are produced in the periphery of the FZ silicon wafer 300a with a slip line 501 or 502. Therefore, the peripheral portion of the silicon wafer with the faulty devices is cut away. This results in degradation in manufacturing yield for the Bi-CMOS semiconductor devices.